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Ordering number : EN*5543
CMOS LSI
LC89051V
Digital Audio Interface Receiver
Preliminary Overview
The LC89051V is for use in IEC958 format data transmission between digital audio equipment. This LSI is used on the receiving side, and handles synchronization with the input signal and demodulation of that signal to a normal format signal.
Package Dimensions
unit: mm 3175A-SSOP24
[LC89051V]
Features
* On-chip PLL circuit synchronizes with the transmitted IEC958 format signal. * Low-voltage operation (3.3 V) * Provides 128fs, bit, and L/R clock outputs. * System clock can be selected to be either 384fs or 512fs. * Microcontroller interface code settings for different output types -- Input pin, emphasis output, input bi-phase data output, and validity flag output settings -- Audio data output format setting -- Channel status output (32-bit output for consumer products) -- Subcode Q output with CRC flags (80 bits) -- Start ID and shortening (skip) ID detection for DAT with subcodes * The built-in VCO can receive at speeds up to twice fs only when operating from a 5-V power supply. * Miniature package: SSOP-24
SANYO: SSOP24
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N3097HA (OT) No. 5543-1/15
LC89051V Pin Assignment
Pin Functions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Symbol DIN1 DIN2 E/DOUT VDD R VIN VCO GND CKSEL XMODE AVOCK TEST1 TEST2 SCLK/CL XLAT/CE SWDT/DI SRDT/DO DQSY/LD CKOUT FS128 BCK LRCK DATAOUT ERROR I/O I I O - I I O - I I I I I I I I O O O O O O O O Description Data input with built-in amplifier (for coaxial or optical module input) Data input (for optical module input) Emphasis, input bi-phase, and validity flag output Power supply VCO gain control input VCO free-running setting input PLL low-pass filter setting Ground System clock selection input (384fs or 512fs) Reset input PLL error lock avoidance clock input Test input (Must be connected to ground in normal operation) Test input (Must be connected to ground in normal operation) Microcontroller interface clock input Microcontroller interface latch/chip enable input Microcontroller interface write data input Microcontroller interface read data output Microcontroller interface subcode Q and ID synchronization output VCO clock output (free running, 384fs, or 512fs) 128fs clock output Bit clock output L/R clock output (left channel = high, right channel = low) Audio data output PLL lock error mute output
No. 5543-2/15
LC89051V Block Diagram
Microcontroller interface
No. 5543-3/15
LC89051V
Specifications
Absolute Maximum Ratings
Parameter Supply voltage I/O voltages I/O current Operating temperature Storage temperature Symbol VDD VI, VO II, IO Topr Tstg Conditions Ratings -0.3 to +7.0 -0.3 to VDD + 0.3 20 -30 to +75 -55 to +125 Unit V V mA C C
Allowable Operating Ranges
Parameter Supply voltage Operating temperature Symbol VDD TOPR Conditions min 3.0 typ 5.0 (3.3) -30 +75 C max 5.5 Unit V
Electrical Characteristics DC Characteristics (1) at Ta = -30 to +75C, VDD = 4.5 to 5.5 V, VSS = 0 V
Parameter Input high-level voltage Input low-level voltage Input high-level voltage Input low-level voltage Input high-level voltage Input low-level voltage Output high-level voltage Output low-level voltage Current drain Input amplitude Note: 1. 2. 3. 4. 5. Symbol VIH1 VIL1 VIH2 VIL2 VIH3 VIL3 VOH VOL IDD Vpp *1 *1 *2 *2 *3 *3 IOH = -4 mA IOL= 4 mA *4 *5 0.4 Conditions min 0.7 VDD -0.3 0.8 VDD -0.3 2.5 -0.3 VDD - 2.1 0.4 20 VDD + 0.3 typ max VDD + 0.3 0.3 VDD VDD + 0.3 0.2 VDD VDD + 0.3 +0.6 Unit V V V V V V V V mA V
Applies to the CKSEL, AVOCK, TEST1, and TEST2 pins. CMOS levels. Applies to the XMODE, SCLK/CL, XLAT/CE, SWDT/DI pins. CMOS Schmitt inputs. Applies to the DIN2 pin. TTL Schmitt levels. VDD = 5.0 V, Ta = 25C, input data fs = 96 kHz Measured before the DIN1 pin input capacitor.
DC Characteristics (2) at Ta = -30 to +75C, VDD = 3.0 to 3.6 V, VSS = 0 V
Parameter Input high-level voltage Input low-level voltage Input high-level voltage Input low-level voltage Input high-level voltage Input low-level voltage Output high-level voltage Output low-level voltage Current drain Input amplitude Note: 6. 7. 8. 9. 10. Symbol VIH1 VIL1 VIH2 VIL2 VIH3 VIL3 VOH VOL IDD Vpp *6 *6 *7 *7 *8 *8 IOH = -2 mA IOL= 2 mA *9 *10 0.4 Conditions min 0.7 VDD -0.3 0.75 VDD -0.3 2.4 -0.3 VDD - 0.8 0.4 10 VDD + 0.3 typ max VDD + 0.3 0.2 VDD VDD + 0.3 0.15 VDD VDD + 0.3 +0.3 Unit V V V V V V V V mA V
Applies to the CKSEL, AVOCK, TEST1, and TEST2 pins. CMOS levels. Applies to the XMODE, SCLK/CL, XLAT/CE, SWDT/DI pins. CMOS Schmitt inputs. Applies to the DIN2 pin. TTL Schmitt levels. VDD = 3.3 V, Ta = 25C, input data fs = 48 kHz Measured before the DIN1 pin input capacitor.
No. 5543-4/15
LC89051V AC Characteristics (Normal Mode) at Ta = -30 to +75C, VDD = 3.0 to 5.5 V
Parameter AVOCK input pulse width VCO free-running frequency BCK output pulse width Output data setup time Output data hold time Output delay Symbol tWBI fVCO tWBO tDSO tDHO tBD *11 *12 fs = 48 kHz 160 80 80 -10 0 +10 Conditions min 10 50 75 typ max Unit s MHz MHz ns ns ns ns
Note: 11.Ta = 25C, VDD = 3.3 V, with the circuit constants for standard speed operation in the sample application circuit. 12.Ta = 25C, VDD = 5.0 V, with the circuit constants for standard speed operation in the sample application circuit.
AC Characteristics (Double Speed Mode) at Ta = -30 to +75C, VDD = 4.5 to 5.5 V
Parameter AVOCK input pulse width VCO free-running frequency BCK output pulse width Output data setup time Output data hold time Output delay Symbol tWBI fVCO tWBO tDSO tDHO tBD *13 fs = 96 kHz 80 40 40 -10 0 +10 Conditions min 10 80 typ max Unit s MHz ns ns ns ns
Note: 13.Ta = 25C, VDD = 5.0 V, with the circuit constants for 2x speed operation in the sample application circuit.
No. 5543-5/15
LC89051V Microcontroller Interface Block AC Characteristics at Ta = -30 to +75C, VDD = 3.0 to 5.5 V (when CKSEL is low)
Parameter CL low pulse width CL high pulse width Data setup time Data hold time CE delay time CL delay time CE delay time LD pulse width Data delay time Data delay time Symbol tWL tWH tDS tDH tD3 tD4 tD5 tW tD1 tD2 fs = 44.1 kHz fs = 88.2 kHz CL = 30 pF CL = 30 pF 136 68 100 100 Conditions min 100 100 50 50 1.0 50 100 typ max Unit ns ns ns ns s ns ns s s ns ns
Input mode
Output mode
No. 5543-6/15
LC89051V Microcontroller Interface Block AC Characteristics at Ta = -30 to +75C, VDD = 3.0 to 5.5 V (when CKSEL is high)
Parameter SCLK low pulse width SCLK high pulse width Setup time Hold time Delay time DQSY pulse width XLAT pulse width Data delay time Data delay time Symbol tWL tWH tDS tDH tD tW tWLA tD1 tD2 CL = 30 pF CL = 30 pF fs = 44.1 kHz fs = 88.2 kHz 100 100 100 Conditions min 100 100 50 50 100 136 68 typ max Unit ns ns ns ns s s s ns ns ns
Input mode
Output mode
No. 5543-7/15
LC89051V Functions 1. Data Input and Output (DIN1, DIN2, E/DOUT) The DIN1 pin has a built-in amplifier, and can receive signals with an amplitude of about 400 mVp-p (coaxial input). The DIN2 pin is only for use in optical modules. Note that although the data input pins are controlled by the microcontroller, DIN1 can be selected when a microcontroller is not used. The microcontroller interface pins must be tied low in such applications. The E/DOUT normally outputs channel status information. However, it can be set to output either the input bi-phase data or the validity flag by command codes from the microcontroller. 2. PLL (R, VIN, VCO, AVOCK) This circuit includes a built-in VCO and supports sampling frequencies of 32, 44.1, and 48 kHz. This LSI can also receive at the 2x sampling frequencies of 64 kHz, 88.2 kHz, and 96 kHz, but only when operating from a 5-V power-supply voltage. However, the demodulated data and clock output during double speed reception follow the received sampling frequency, and the transmission format for 2x-speed data must follow the IEC958 standard. The built-in VCO is controlled by the resistors connected to the R and VIN pins. The resistor connected to R functions as both the VCO gain control and as temperature compensation. The VIN pin sets the VCO free-running frequency. Recommended circuit constants are shown in the sample application circuit. Note that the VCO free-running frequency varies with temperature and with manufacturing variations between samples. The recommended circuit constants shown in the sample application circuit take these variations into account so that the PLL circuit lockup characteristics are not adversely affected. These values are not designed to reduce variations in the free-running frequency. The VCO pin is the PLL loop filter pin. The loop filter is formed by attaching an external capacitor and a resistor to this pin. See the sample application circuit for these circuit constants.
PLL Loop Filter Structure
The PLL circuit will be reset within a fixed period when PLL lock pull-in fails if a continuously operating clock of no more than 50 kHz is input to the AVOCK pin. This allows incorrect PLL operation to be avoided. 3. Clock Settings and Output (FS128, BCK, LRCK, DATAOUT, CKSEL, CKOUT) A 128fs clock signal is output from the FS128 pin. Figure 1 shows the output timing for the BCK, LRCK, and DATAOUT pins. The CKOUT clock output is set by the CKSEL pin as listed in the table below.
CKSEL L H CKOUT 384fs clock output 512fs clock output
The microcontroller interface format is also set by CKSEL as listed in the table below.
CKSEL L H Microcontroller interface Figure 2 Figure 3
No. 5543-8/15
LC89051V
Figure 1 Data Output Timing
No. 5543-9/15
LC89051V
Figure 2 Microcontroller Interface Timing 1
No. 5543-10/15
LC89051V
Figure 3 Microcontroller Interface Timing 2
No. 5543-11/15
LC89051V Microcontroller Interface (SCLK/CL, XLAT/CE, SWDT/DI, SRDT/DO, DQSY/LD) 1. Data input and output addresses are allocated as follows:
Data input or output Data input C bit output Subcode Q, ID output F7 F8 F9 Figure 2: Microcontroller Interface Timing 1 B0 1 0 1 B1 1 0 0 B2 1 0 0 B3 0 1 1 A0 1 1 1 A1 1 1 1 A2 1 1 1 A3 1 1 1 EA E9 E8 Figure 3: Microcontroller Interface Timing 2 B0 0 1 0 B1 1 0 0 B2 0 0 0 B3 1 1 1 A0 0 0 0 A1 1 1 1 A2 1 1 1 A3 1 1 1
2. The input command codes control the following setting: * System stop * Data input pin setting * Input bi-phase data output selection * Validity flag output selection * Audio data output format setting DI1: Stops VCO operation and thus stops the system.
DI1 System L Operating H Stopped
DI2: Selects which input data to demodulate.
DI2 Data demodulation input L DIN1 H DIN2
DI3 and DI4: Select the E/DOUT pin output.
DI3 DI4 E/DOUT L Emphasis data output L H Validity flag output L DIN1 input data output H H DIN2 input data output
DI5 and DI6: Set the audio data output format.
DI5 DI6 DATAOUT L L H L 20-bit rightjustified MSB first H H 20-bit leftjustified MSB first
16-bit right- 20-bit rightjustified justified MSB first LSB first
All bits are set low immediately after XMODE is switched from low to high. DI0 and DI7 are not used.
No. 5543-12/15
LC89051V 3. The following output settings can be controlled: * Channel status (C bit) output * Subcode Q data output * Start ID and shortening ID detection for DAT with subcodes C bit output * This IC only handles the first 32 bits. * The flag is fixed at the high level (only when CKSEL is high), and the data format is LSB first. * Error and update checking is not applied to the data. * The internal shift register is reset if a PLL lock error occurs. * Since the channel status information consists of 192 frames, a fixed period must be provided between data readout operations. 1 x 192 (ms) < (the interval between data readout operations) fs Subcode Q output * Subcode Q can be read out after the fall of the DQSY/LD signal. Also note that the data is updated every time this signal falls. However, this signal will not be output (fall) unless 96-bit subcode Q data (including the CRC check bits) is input. * The flag outputs a high when the CRC check passes, and low if the CRC check fails. Besides, the shift clock SCLK is required to be input regardless of the CRC flag status after latch pulse input. * The bit order is LSB first within each byte of the 80 bits of subcode Q data. ID detection * The start ID and shortening ID are only detected when the DAT category code (1100000L) is received. * These IDs are detected as follows: -- A low pulse is output from DQSY/LD if a start ID (R0) or a shortening ID (L1) is detected following a sync signal (L0). -- After this signal, data can be read out from SRDT/DO by inputting the same address value as that used for subcode Q data to SWDT/DI.
Figure 4 User Data for DAT with Subcodes * The table below shows the relationship between the sync signal (L0), the start ID (R0), the shortening ID (L1), and the data output.
(L0): SYNC (R0): Start ID (L1): Shortening ID Flags + 80 data bits Detected ID H H L all H Start ID H L H all L Shortening ID
* Output pins The output scheme used for SRDT/DO differs depending on the microcontroller interface format selected by
CKSEL L H Format Figure 2 Figure 3 SRDT/DO High open-drain output Three-state output
No. 5543-13/15
LC89051V Error (ERROR) The ERROR pin goes high if there is an error in the input data or if the PLL is unlocked. It holds the high level for about 100 to 300 ms after data demodulation returns to normal and then goes low. The table below lists the data processing when an error has occurred.
Type of error Up to 8 consecutive parity errors Over 8 consecutive parity errors PLL lock error DATAOUT Previous data value L L C bit Output Output L Sub Q Output Output L ID Output Output L E/DOUT Output Output L
System Reset (XMODE) Normal system operation is started by setting XMODE high after the power supply has risen above at least 4.5 V (3.0 V). After power is applied, the system will be reset if a low level is applied once more to the XMODE pin. If XMODE is set low, the VCO free-running oscillator clock is output from CKOUT.
Figure 5 XMODE Pin Operation
No. 5543-14/15
LC89051V Sample Application Circuit
Circuit constants
Value Item Symbol 5.0-V operation Standard speed R1 Resistors R2 R3 R4 Capacitors C1 C2 24 k 5.1 k 5.1 k 150 0.1F 0.01 F 2x speed 24 k 5.1 k 12 k 150 0.1F 0.01 F 3.3-V operation Standard speed 24 k 5.1 k 5.1 k 150 0.1F 0.01 F
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of November, 1997. Specifications and information herein are subject to change without notice. No. 5543-15/15

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